Method of making tungsten local interconnect using a silicon nitride capped self-aligned contact process

ABSTRACT

A process for fabricating MOSFET devices, using a local interconnect structure, and silicon nitride capped, self-aligned contact openings, has been developed. The process features the creation of self-aligned contact openings, exposing specific source and drain regions. After deposition of a composite insulator layer, a second opening is formed in the composite insulator layer, again exposing various elements including the previously opened, specific source and drain regions. The formation of a local interconnect structure, filling the second opening, contacts, as well as interconnects, the specific source and drain regions.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to the fabrication of semiconductordevices, and more specifically to a fabrication sequence used createmetal oxide semiconductor field effect transistor, (MOSFET), devices,featuring local interconnects, and self-aligned contact, (SAC),structures.

(2) Description of Prior Art

The semiconductor industry is continually striving to improve theperformance of semiconductor devices, while still attempting to reducethe cost of these same devices. These objectives have been successfullyaddressed by the ability of the semiconductor industry to practicemicro-miniaturization, or to fabricate semiconductor devices withsub-micron features. Several fabrication disciplines, such asphotolithography, as well as dry etching, have allowedmicro-miniaturization to be realized. The use of more sophisticatedexposure cameras, as well as the use of more sensitive photoresistfilms, have allowed the attainment of sub-micron images in photoresistfilms, to be routine achieved. In addition, the development of moreadvanced dry etching tools and processes, have allowed the sub-micronimages, in masking photoresist films, to be successfully transferred tounderlying materials used for the fabrication of semiconductor devices.

In addition to advances in semiconductor fabrication disciplines,several device structural innovations have also contributed to the questfor higher performing, lower cost, semiconductor devices. For examplethe use of a self-aligned contact, (SAC), procedure, allows the amountof source and drain contact area to be reduced, thus allowing smallerdevices to be constructed, resulting in faster, as well as lower costdevices, to be realized. The SAC procedure, using a sub-micron groundrule, opens a sub-micron region in an insulator layer, exposing anunderlying source and drain region. However only a portion of thesub-micron SAC opening is used to expose the underlying source and drainregion, with the remainder of the sub-micron SAC opening overlapping anadjacent polysilicon gate structure. Therefore the source and draincontact region is smaller then the SAC opening. If the contact openingto the source and drain was to made entirely overlaying the source anddrain region, the source and drain region would have to be designedlarger, to accommodate the fully landed contact hole opening, thusresulting in a undesirable, larger semiconductor device.

Local interconnect structures, used as a partial, or an M_(o) wiringlevel, can also be used to reduce cost, while improving the density, ofadvanced MOSFET devices. The use of a metal, or of a metal silicidestructure, contacting, and connecting, underlying active regions ofseveral MOSFET devices, can result in the desired cell wiring,accomplished using a short, and therefore low resistance,interconnection. This invention will describe a novel process, usingsilicon nitride capped, SAC processes, in conjunction with a localinterconnect process, used to obtain the desired integration of MOSFETdevices. Prior art such as Ramaswami, et al, in U.S. Pat. No. 5,451,545,describe a local interconnect process, but this art does not use the SACprocess needed for micro-miniaturization. In addition Ramaswami, et al,describe a process for interconnecting a gate structure to a source anddrain region, of a specific MOSFET device, while the present inventionwill describe a process for connecting elements of various MOSFETdevices.

SUMMARY OF THE INVENTION

It is an object of this invention to use a novel process to fabricate alocal interconnect structure, for MOSFET devices.

It is another object of this invention to use a self-aligned contact,(SAC), process, to create openings to source and drain regions, of theMOSFET devices.

It is still another object of this invention to use a double, siliconnitride capping procedure, to allow a local interconnect structure tointerface, and to interconnect, specific source and drain regions, inone area of a MOSFET cell, to other source and drain regions, located inanother area of the MOSFET cell, with the source and drain regionsexposed in SAC openings.

In accordance with the present invention a process for integratingMOSFET device structures, using a new local interconnect, and doublesilicon nitride capped, SAC opening, is described. A field oxide regionis created in a semiconductor substrate, followed by the creation offour polysilicon gate structures, with a first polysilicon gatestructure, and a second polysilicon gate structure, located in a firstregion of the semiconductor substrate, and with a third polysilicon gatestructure, and a fourth polysilicon gate structure, located in a secondregion of the semiconductor substrate, with the field oxide regionseparating the regions. The polysilicon gate structures are comprised ofa metal silicide--polysilicon layer, underlying a capping insulatorlayer, and overlying a thin gate insulator layer. Lightly doped sourceand drain regions are formed, followed by the creation of an insulatorspacer, on the sides of all polysilicon gate structures. Heavily dopedsource and drain regions are next formed between the first and secondpolysilicon gate structures, between the third and fourth polysilicongate structures, between the second polysilicon gate structure and fieldoxide region, and between the third polysilicon gate structure and thefield oxide region. A first silicon nitride layer is deposited andpatterned to create SAC openings, with one SAC opening exposing thesource and drain region between the first and second polysilicon gatestructures, while a second SAC opening exposes the source and drainregion between the third and the fourth polysilicon gate structures. TheSAC openings are larger in width than the space between polysilicon gatestructures, therefore the SAC openings also expose a portion of the topsurface of the capping insulator layer, on the polysilicon gatestructures. A second silicon nitride layer, as well as a interleveldielectric layer, are next deposited. Patterning to create the openingfor the local interconnect structure is next performed, first by removalof the interlevel dielectric layer, with the etching procedureterminating on the second silicon nitride layer, and followed by removalof the second silicon nitride layer, again exposing the source and drainregions between the first and the second polysilicon gate structures, aswell as exposing the source and drain region between the third andfourth polysilicon gate structures. Deposition of an adhesive layer, abarrier layer, and a thick metal layer, are performed, followed byremoval of unwanted metal, barrier and adhesive layers, resulting in thelocal interconnect structure, in the local interconnect opening, andproviding the connection of the source and drain region, between thefirst and second polysilicon gate structures, to the source and drainregion, between the third and fourth polysilicon gate structures.

BRIEF DESCRIPTION OF THE DRAWINGS

The object and other advantages of this invention are best described inthe preferred embodiments with reference to the attached drawings thatinclude:

FIGS. 1-7, which schematically, in cross-sectional style, describe theProcess used to fabricate MOSFET devices, using a SAC opening, and alocal interconnect process, to connect source and drain regions from onearea of a MOSFET cell, to source and drain regions located in anotherregion of the MOSFET cell.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The method of fabricating MOSFET devices, featuring SAC openings and alocal interconnect structure, and used to interconnect various regionsof a MOSFET cell, will now be covered in detail. In this description theMOSFET device described will be a N channel, (NFET), device. Howeverthis invention can also be used with P channel, (PFET), devices, orcomplimentary, (CMOS), devices, comprised of both PFET and NFET devices.

FIG. 1, schematically shows the early stages of fabrication of thisinvention. A P type semiconductor substrate 1, with a <100>crystallographic orientation, is used. Field oxide, (FOX), region 2, isformed for isolation purposes, as well as to provide a base for asubsequent capacitor structure to be fabricated on. FOX region 2, isformed via thermal oxidation, of exposed semiconductor substrate 1, inan oxygen--steam ambient, at a temperature between about 850° to 1050°C., to a thickness between about 3000 to 5000 Angstroms. Subsequentdevice regions, or regions not converted to FOX region 2, are protectedby a masking pattern of an oxidation resistant composite layer,comprised of an overlying silicon nitride layer, on an underlying padsilicon oxide layer. The desired masking pattern, of the oxidationresistant composite layer, is obtained via conventionalphotolithographic and dry etching procedures. After formation of the FOXregion 2, the masking pattern is removed, using hot phosphoric acid forsilicon nitride, and a buffered hydrofluoric acid solution for the padoxide. A gate insulator layer 3, comprised of silicon dioxide, is nextformed via thermal oxidation, in an oxygen--steam ambient, at atemperature between about 850° to 1000° C., to a thickness between about50 to 200 Angstroms. A polycide layer 4, is next deposited, comprised ofan underlying, N type, in situ doped polysilicon layer, deposited to athickness between about 1000 to 2000 Angstroms, and followed by thedeposition of tungsten silicide layer, at a thickness between about 500to 1500 Angstroms. A capping insulator layer 5, of silicon oxide is nextdeposited using either LPCVD or plasma enhanced chemical vapordeposition, (PECVD), to a thickness between about 1000 to 3000Angstroms. Capping insulator layer 5, can also be a silicon nitridelayer.

The capping insulator layer--polycide composite is next patterned toform polysilicon gate structures, shown schematically in FIG. 1. Thepatterning is accomplished using conventional photolithographicprocedures, and using anisotropic reactive ion etching, (RIE), whereCHF₃ is used as an etchant for capping insulator layer 5, while Cl₂ isused as an etchant for the polycide layer 4. Polysilicon gate structure30, and polysilicon gate structure 31, are formed to the left of FOXregion 2, while polysilicon gate structure 32, and polysilicon gatestructure 33, are formed to the right of FOX region 2. Polysilicon gatestructure 40, is formed on FOX region 2. Lightly doped source and drainregions 6, are next formed in regions not covered by polysilicon gatestructures, or FOX region 2, via ion implantation of either arsenic orphosphorous, at an energy between about 20 to 80 KeV, at a dose betweenabout 7×10¹³ to 3×10⁷⁴ atoms/cm². An insulator layer of silicon oxide isnext deposited, using either LPCVD or PECVD procedures, to a thicknessbetween about 1000 to 2000 Angstroms, and subjected to an anisotropicRIE procedure, using CHF₃ as an etchant, creating insulator spacers 7,schematically shown in FIG. 1. Insulator spacers 7, can also be formedfrom a silicon nitride layer. Heavily doped source and drain regions 8,are than formed, in regions of semiconductor substrate 1, not covered byeither polysilicon gate structures, or by insulator spacers 7, via ionimplantation of either arsenic or phosphorous at an energy between about25 to 80 KeV, at a dose between about 1×10¹⁵ to 6×10¹⁵ atoms/cm².

A first silicon nitride layer 9, is deposited using LPCVD or PECVDprocedures, to a thickness between about 600 to 1000 Angstroms. Aphotoresist shape 10, with an opening exposing the source and drainregion between polysilicon gate structure 30, and polysilicon gatestructure 31, and with an opening exposing the source and drain regionbetween polysilicon gate structure 32, and polysilicon gate structure33, is formed. These openings are larger in width than the space betweenpolysilicon gate structures, therefore these openings also expose aportion of first silicon nitride layer 9, overlying the polysilicon gatestructures. An anisotropic RIE procedure, using CHF₃ and argon as anetchant, is next performed removing the portions of first siliconnitride layer 9, exposed in the openings in photoresist shape 10, andcreating SAC openings 20, shown schematically in FIG. 2. SAC openings20, or the width of exposed source and drain regions, between theinsulator spacer coated, polysilicon gate structures, is between about0.30 to 0.80 μM. Photoresist shape 10, is removed via plasma oxygenashing and careful wet cleans.

A second silicon nitride layer 11, is deposited using LPCVD or PECVDprocedures, to a thickness between about 200 to 400 Angstroms. Aninterlevel dielectric layer 12, (ILD), is then deposited, comprised ofundoped plasma enhanced silicon oxide, (PETEOS), deposited to athickness between about 1000 to 2000 Angstroms, usingtetraethylorthosilicate, (TEOS), as a source, and followed by anoverlying layer of boro-phosphosilicate glass, (BPTEOS), layer,deposited to a thickness between about 3000 to 12000 Angstroms. Ananneal is next performed at a temperature between about 750° to 900° C.,to reflow ILD layer 12, resulting in the smooth top surface,schematically shown in FIG. 3.

Photoresist shape 13, is next formed, featuring an opening exposing thearea between polysilicon gate structure 30, and polysilicon gatestructure 33. This opening will define the local interconnect region. Ananisotropic RIE procedure, using CHF₃ as an etchant is used to removeILD layer 12, exposed in the opening in photoresist shape 13. This RIEprocedure offers the selectivity needed to prevent etching of secondsilicon nitride layer 11, after removal of ILD layer 12. This isschematically shown in FIG. 4. Another anisotropic RIE procedure isperformed, using CHF₃ and argon as an etchant, and used to remove secondsilicon nitride layer 11, exposed in the opening in photoresist shape13. The result of this RIE procedure, schematically shown in FIG. 5,again results in SAC openings 20, exposing a source and drain regionbetween polysilicon gate structure 30, and polysilicon gate structure31, and exposing a source and drain region between polysilicon gatestructure 32 and polysilicon gate structure 33. Removal of photoresistshape is again accomplished via plasma oxygen ashing and careful wetcleans.

A composite layer 14, comprised of an underlying adhesive layer oftitanium, and an overlying barrier layer of titanium nitride, isdeposited using r. f. sputtering procedures, to a composite thicknessbetween about 500 to 1500 Angstroms. A layer of tungsten 15, is thendeposited, using LPCVD procedures, at a temperature between about 375°to 500° C., to a thickness between about 4000 to 7000 Angstroms, usingtungsten hexafluoride and silane as a source, and completely filling theopening in ILD layer 12. The composite layer 14, and the overlyingtungsten layer 15, directly contact the source and drain regions,exposed in SAC openings 20. This is schematically shown in FIG. 6.Tungsten layer 15, can be replaced by other conductive layers, such asmolybdenum, doped polysilicon, or metal silicides. Regions of unwantedcomposite layer 14, and tungsten layer 15, overlying ILD layer 12, arenext removed using an anisotropic RIE procedure, using SF₆ as anetchant, resulting in tungsten plug 15, in the ILD opening. The removalof these layers can also be accomplished using a chemical mechanicalpolishing, (CMP), procedure. This is schematically shown in FIG. 7. Theconductive plug, comprised of composite layer 14, and tungsten layer 15,connects the source and drain region, between polysilicon gate structure30, and polysilicon gate structure 31, to a source and drain region,between polysilicon gate structure 32, and polysilicon gate structure33. This local interconnect structure allows the integration of theseelements, at a local level, reducing subsequent topography concerns,which could occur if this connection were to realized using upper metallevels.

While this invention has been particularly shown and described withreference to, the preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made without departing from the spirit and scope of this invention.

What is claimed is:
 1. A method of integrating elements of MOSFETdevices, on a semiconductor substrate, via the use of a localinterconnect structure, comprising the steps of:forming a field oxideregion in said semiconductor substrate; forming a first polysilicon gatestructure, and a second polysilicon gate structure, on a gate insulatorlayer, in a first region of said semiconductor substrate, and forming athird polysilicon gate structure, and a fourth polysilicon gatestructure, on a gate insulator layer, in a second region of saidsemiconductor substrate, with said first region of said semiconductorsubstrate, and said second region of said semiconductor substrate,separated by said field oxide region; forming insulator sidewall spacerson the sides of the polysilicon gate structures; forming a first sourceand drain region, in a first region of said semiconductor substrate,between said first polysilicon gate structure, and said secondpolysilicon gate structure, and forming a second source and drainregion, in said second region of said semiconductor substrate, betweensaid third polysilicon gate structure, and said fourth polysilicon gatestructure; depositing a first insulator layer, on all polysilicon gatestructures, on all insulator sidewall spacers, and on all source anddrain regions; forming a self-aligned contact, (SAC), opening, in saidfirst insulator layer, exposing said first source and drain region, insaid first region of said semiconductor substrate, and forming a SACopening in said first insulator layer, exposing said second source anddrain region, in said second region of said semiconductor substrate;depositing a second insulator layer, on said first insulator layer, andon said first source and drain region, and on said second source anddrain region, exposed in SAC openings; forming a local interconnectopening in said second silicon insulator layer, exposing said firstsource and drain region, and said second source and drain region; andforming a local interconnect structure, in said local interconnectopening, contacting said first source and drain region, and said secondsource and drain region.
 2. The method of claim 1, wherein said gateinsulator layer is silicon dioxide, thermally grown, in an oxygen-steamambient, at a temperature between about 850° to 1000° C., to a thicknessbetween about 50 to 200 Angstroms.
 3. The method of claim 1, whereinsaid polysilicon gate structures are a polycide layer, comprised of anunderlying, N type, in situ doped, polysilicon layer, at a thicknessbetween about 1000 to 2000 Angstroms, and an overlying tungsten silicidelayer, at a thickness between about 500 to 1500 Angstroms, and cappedwith an overlying insulator layer of either silicon oxide, or siliconnitride, at a thickness between about 1000 to 3000 Angstroms.
 4. Themethod of claim 1, wherein said first source and drain regions, and saidsecond source and drain regions, are formed via ion implantationprocedures, using either arsenic or phosphorous, at an energy betweenabout 25 to 80 KeV, at a dose between about 1×10¹⁵ to 6×10¹⁵ atoms/cm².5. The method of claim 1, wherein said first insulator layer is asilicon nitride layer, deposited using either LPCVD or PECVD procedures,to a thickness between about 600 to 1000 Angstroms.
 6. The method ofclaim 1, wherein said SAC opening, is formed via anisotropic etching ofsaid first insulator layer, using CHF₃ and argon as an etchant, creatingan opening between about 0.3 to 0.8 micrometer, in the spaces betweensaid polysilicon gate structures, exposing said first source and drainregion, and said second source and drain region.
 7. The method of claim1, wherein said second insulator layer is comprised of an underlyingsilicon nitride layer, at a thickness between about 200 to 400Angstroms, and an overlying composite layer, comprised of a BPTEOSlayer, at a thickness between about 3000 to 12000 Angstroms, overlyingan undoped PETEOS layer, at a thickness between about 1000 to 2000Angstroms.
 8. The method of claim 7, wherein said local interconnectopening is formed in said second insulator layer via anisotropic RIEprocedures, using CHF₃ as an etchant for the BPTEOS and PETEOS layers,while CHF₃ and argon is used as an etchant for silicon nitride.
 9. Themethod of claim 1, wherein said local interconnect structure isdeposited using LPCVD or r.f. sputtering procedures, to a thicknessbetween about 4000 to 7000 Angstroms, and an underlying composite layer,comprised of titanium nitride layer on a titanium layer, deposited usingr.f. sputtering procedures, at a thickness between about 500 to 1500Angstroms.
 10. The method of claim 1, wherein said local interconnectstructure is formed via anisotropic RIE procedures, using SF₆ as anetchant.
 11. The method of claim 1, wherein said local interconnectstructure is formed via chemical mechanical polishing procedures.
 12. Amethod for connecting elements of MOSFET devices, on a semiconductorsubstrate, via use of a self-aligned, local interconnect structure,formed using silicon nitride capping SAC processing, comprising thesteps of:forming a field oxide region in said semiconductor substrate;forming a first polysilicon gate structure, and a second polysilicongate structure, on a gate insulator layer, in a first region of saidsemiconductor substrate, and forming a third polysilicon gate structure,and a fourth polysilicon gate structure, on a gate insulator layer, in asecond region of said semiconductor substrate, with said first region ofsaid semiconductor substrate, and said second region of saidsemiconductor substrate, separated by said field oxide region; forminginsulator sidewall spacers on the sides of the polysilicon gatestructures: forming a first heavily doped source and drain region insaid first region of said semiconductor substrate, between said firstpolysilicon gate structure, and said second polysilicon gate structure,and forming a second heavily doped source and drain region in saidsecond region of said semiconductor substrate, between said thirdpolysilicon gate structure, and said fourth polysilicon gate structure;depositing a first silicon nitride layer on said polysilicon gatestructures, on said insulator sidewall spacers, and on said heavilydoped source and drain regions; forming a SAC opening, in said firstsilicon nitride layer, exposing said first heavily doped source anddrain region, and forming a SAC opening, in said first silicon nitridelayer, exposing said second heavily doped source and drain region;depositing a second silicon nitride layer, on said first silicon nitridelayer, and on said first heavily doped source and drain region, and onsaid second heavily doped source and drain region, exposed in the SACopenings; depositing a composite interlevel dielectric layer on saidsecond silicon nitride layer; forming a local interconnect opening insaid interlevel dielectric layer, and in said second silicon nitridelayer, exposing said first heavily doped source and drain region, andsaid second heavily doped source and drain region; depositing acomposite layer of an underlying adhesive layer, and an overlyingbarrier layer, in said local interconnect opening; depositing a tungstenlayer, the overlying barrier layer, of said composite layer; and anoverlying; and patterning of said tungsten layer, and of said compositelayer, to form said self-aligned local interconnect structure,contacting said first heavily doped source and drain region, and saidsecond heavily doped source and drain region.
 13. The method of claim12, wherein said gate insulator layer is silicon dioxide, thermallygrown in an oxygen-steam ambient, at a temperature between about 850 to1000° C., to a thickness between about 50 to 200 Angstroms.
 14. Themethod of claim 12, wherein polysilicon gate structures are a polycidelayer, comprised of an underlying, N type, in situ doped polysiliconlayer, at a thickness between about 1000 to 2000 Angstroms, and anoverlying tungsten silicide layer, at a thickness between about 500 to1500 Angstroms, and with said polysilicon gate structures capped with anoverlying silicon oxide layer, deposited using TEOS as a source, to athickness between about 1000 to 3000 Angstroms.
 15. The method of claim12, wherein heavily doped source and drain regions are formed via ionimplantation of either arsenic or phosphorous, at an energy betweenabout 25 to 80 KeV, at a dose between about 1×10¹⁵ to 6×10¹⁵ atoms/cm².16. The method of claim 12, wherein said first silicon nitride layer isdeposited using LPCVD or PECVD procedures, to a thickness between about600 to 1000 Angstroms.
 17. The method of claim 12, wherein said SACopening, in said first silicon nitride layer, is formed via anisotropicRIE procedures, using CHF₃ and argon as an etchant, creating a spacebetween about 0.3 to 0.8 micrometer, in width, between polysilicon gatestructures, and exposing said first heavily doped source and drainregion, and said second heavily doped source and drain region.
 18. Themethod of claim 12, wherein said second silicon nitride layer, isdeposited using LPCVD or PECVD procedures, to a thickness between about200 to 400 Angstroms.
 19. The method of claim 12, wherein said compositeinterlevel dielectric layer is comprised of an underlying, undopedPETEOS layer, at a thickness between about 1000 to 2000 Angstroms, andan overlying BPTEOS layer, at a thickness between about 3000 to 12000Angstroms.
 20. The method of claim 12, wherein said local interconnectopening is formed via anisotropic RIE of said composite interleveldielectric layer, using CHF₃ as an etchant, and via anisotropic RIE ofsaid second silicon nitride layer, using CHP₃ as an etchant.
 21. Themethod of claim 12, wherein composite adhesive and barrier layer isdeposited using r.f. sputtering, to a thickness between about 500 to1500 Angstroms, comprised of an underlying titanium adhesive layer, andan overlying titanium nitride barrier layer.
 22. The method of claim 12,wherein said tungsten layer is deposited using LPCVD procedures, to athickness between about 4000 to 7000 Angstroms.
 23. The method of claim12, wherein said self-aligned local interconnect structure is formed viaanisotropic RIE of said tungsten layer, and of said composite adhesiveand barrier layer, using SF₆ as an etchant.